Shallow trench isolations present another formidable challenge in the manufacturing of semiconductor chips as the devices approach even smaller submicron ranges. The manufacturing of a semiconductor chip starts with forming a single device on a silicon substrate and isolating the single device from other devices. These individual devices are electrically interconnected through a selected conductive path. The interconnections of these devices are constructed to form the desire circuit functions on a semiconductor chip.
At present, several types of isolation techniques have been proposed, such as LOCOS (LOCal Oxidation of Silicon), LOCOS-base isolation, and shallow trench isolation (STI). A trench isolation is used primarily for isolating devices in VLSI and ULSI, and hence they replace conventional LOCOS isolation techniques. As device geometry reaches submicron size, conventional LOCOS isolation techniques limits the capability to manufacture devices at these small dimensions. For example, the conventional LOCOS structure and shape cause unacceptably large encroachment of the field oxide into the device active regions. Further, the topography of the LOCOS is inadequate for submicron devices. Thus, shallow trench isolation is gaining popularity for quarter-micron technology. In the basic shallow trench isolation (STI) technology, shallow trenches are anisotropically etched into the silicon substrate. A CVD oxide is deposited onto the substrate and is then planarized by CMP (Chemical Mechanical Polishing) or etching back.
One of the problems associated with the formation of STI is dishing effect on a wide trench region. The dishing effect degrades the planarity of a layer, and impacts the control of implantation during the implantation process. In order to overcome this problem during the formation of a shallow trench isolation, a plurality of protrudent portions of the silicon oxide 4 are generated over the trench region 2. This structure is referred to as "reverse tone", as shown in FIG. 1. The protruded portions eliminate the dishing problem from the fast removing rate of the CMP performed over the trench in comparison to the neighboring regions.
However, conventional methods may cause damage of the reverse tone that occurs in misalignment during the formation of the reverse tone. Turning to FIG. 2, a photoresist 6 is patterned on the oxide layer 4 used to form the reverse tone. Since the photoresist 6 is misaligned, a portion of the reverse tone is etched. A portion of the oxide 4 in the trench for isolation is then removed using the photoresist 6 as a mask. The oxide 4 may fail to serve as sufficient isolations between devices. In ULSI, a tiny amount of leakage per device can induce significant power dissipation to the overall circuit.